As is known in the art, CMOS transistors are sometimes formed in a silicon layer disposed on an insulator substrate. In one structure, the fabrication of these CMOS devices is performed on a wafer having a thickness of about 725 microns, doped silicon substrate with a <100> crystallographic orientation. The wafer has a 1400-2000 thick silicon dioxide layer on the upper surface of the substrate and a 1-2 micron thick single crystal silicon layer on the silicon dioxide layer. The wafer is processed to form CMOS transistors in the upper silicon layer. The use of the doped substrate is used to reduce wafer breakage.
As is also known in the art, it is sometimes desirable to form III-V devices on a substrate as a Monolithic Microwave Integrated Circuit (MMIC). In one such structure, a silicon wafer, for example an eight inch silicon wafer of <111> silicon having a thickness of about 725 microns has a layer of III-V material, such as GaN formed on the upper surface using MOCVD or MBE. In the MMIC, microstrip transmission lines are sometimes used to interconnect active, such FET devices, and passive devices formed on, or in, the III-V layer. In such case, after forming the FET and strip conductors from the microstrip transmission lines, the 725 micron thick wafer must be thinned or polished to 50-100 microns for the microstrip transmission line ground plane conductor which will be formed on the backside of the wafer and to accommodate conducive vias which pass from the ground plane to electrodes of the FET. The process of thinning or polishing the backside of the wafer and formation of the vias from the backside of the wafer, however, are difficult to control. Additionally, the high resistance <111> silicon needed for low loss high frequency transmission lines suffers higher wafer breakage. This is due to the fact that the low oxygen content of the Si needed for high resistance (>500 Ohm-cm) makes the Si wafer more brittle.